1. Field of the Invention
The present invention relates in general to a process for fabricating high voltage metal-oxide semiconductor field-effect transistor (MOSFET) devices. In particular, the present invention relates to a process for fabricating high-voltage MOSFET devices having increased breakdown voltage and decreased device die surface area requirement.
2. Technical Background
One of the operating characteristics of MOSFET devices is the breakdown voltage. Conventional MOSFET devices compromise the breakdown voltage with the device semiconductor physical dimensions. In other words, to optimize the acceptable breakdown voltage for a particular MOSFET design, the physical dimension of the device has to be enlarged. A large MOSFET dimension, however, goes against the requirements of device miniaturization. A brief review of the semiconductor structural configuration of a conventional MOSFET device helps to clarify this phenomenon.
FIG. 1 schematically shows the cross-sectional view of a conventional MOSFET. As seen in the drawing, the typical MOSFET comprises an N.sup.+ drain region 110 located below the N.sup.- drift region 120 in the substrate of the device. P-type well 130 is formed at the designated locations of the substrate into the predetermined depth within the confinement of the drift region 120. Each of the N.sup.+ source regions 140 is formed within the confinement of the respective P-type well 130. A gate oxide layer 150 is then formed on the surface of the device substrate and straddles the space between the two separated N.sup.+ source regions 140. The gate 160 further atop the gate oxide layer 150, and both the N.sup.+ source regions 140 and P-channel 130 are brought into external contact by the contact metals 170. Insulating layers 180 further confine-the edges of the contact metals 170 at both sides of the MOSFET device. Arrows identified by the symbol I.sub.e indicate the flow of electrons in the MOSFET device, starting in the N.sup.+ source regions 140 via the P-type well 130 and into the N.sup.+ drain region 110.
Such a configuration for the MOSFET device has its N.sup.+ source regions 140, P-type well 130, and portions of the N.sup.- drift region 120 arranged in the same horizontal plane, which has an expanded die area for the device. An expanded device surface area implies a reduced device density when the device is fabricated on a semiconductor substrate. On the other hand, due to the fact that there is only a portion of the N.sup.- drift region 120 that is placed under the gate 160 as spaced apart via the gate oxide layer 150, the device breakdown voltage is therefore constrained.